title,doi,url,abstract,journal,publication_year,pmid,arxiv
High-Speed and Low Delay Parallel Prefix Adder with Skip Logic, https://doi.org/10.32628/IJSRCSEIT, https://ijsrcseit.com/CSEIT1831301, A carry skip adder (CSKA) structure is presented which has lower power consumption with a higher speed. The performance of the conventional CSKA is improved by achieving the speed enhancement by applying concatenation and incrementation schemes. The existed structure utilizes AND-OR-INVERT (AOI) and OR-AND-INVERT (OAI) compound gates for the skip logic. Low power very large scale integration (VLSI) circuits are most significant for designing of high performance and portable devices. The high speed small area and low cost are the main considerations of VLSI circuits. This paper presents the design and hardware implementation of Hybrid variable latency CSKA. The proposed design is simulated using ISE simulator. The design shows 38% improvement in speed and 11.53% improvement in area compared to carry look ahead adder. The maximum power consumption for proposed system is 0.014W., International Journal of Scientific Research in Computer Science Engineering and Information Technology, 2018, CSEIT1831301