@article{IJSRCSEIT,
  title={Realization of Redundant Binary Multiplier with Modified Partial Product Generator Using Verilog},
  author= {{V. Lakshma Reddy} and { H. Sudhakar} and { D. Ajay Kumar}},
  journal={International Journal of Scientific Research in Computer Science, Engineering and Information Technology},
  volume={2},
  url={https://ijsrcseit.com/CSEIT1726264},
  year={2017},
  publisher={Technoscience Academy}
}