TY  - JOUR
TI  - Realization of Redundant Binary Multiplier with Modified Partial Product Generator Using Verilog
AU  - V. Lakshma Reddy
AU  -  H. Sudhakar
AU  -  D. Ajay Kumar
JO  - International Journal of Scientific Research in Computer Science, Engineering and Information Technology
PB  - Technoscience Academy
DA  - 2017/12/31
PY  - 2017
DO  - https://doi.org/10.32628/IJSRCSEIT
UR  - https://ijsrcseit.com/CSEIT1726264
VL  - 2
IS  - 6
SP  - 924	
EP  - 929
AB  - Digital multipliers are widely used in arithmetic units of microprocessors, multimedia and digital signal processors. A redundant binary (RB) representation can be used when designing high performance multipliers due to its high modularity and carry-free addition. The conventional RB multiplier requires an additional RB partial product (RBPP) row, because an error-correcting word (ECW) is generated by both the radix-4 Modified Booth encoding (MBE) and the RB encoding. This incurs in an additional RBPP accumulation stage for the MBE multiplier. In this paper, a new RB modified partial product generator (RBMPPG) is proposed; it removes the extra ECW and hence, it saves one RBPP accumulation stage. Therefore, the proposed RBMPPG generates fewer partial product rows than a conventional RB MBE multiplier. Simulation results show that the proposed RBMPPG based designs significantly improve the area and power consumption when the word length of each operand in the multiplier is at least 32 bits.