TY  - JOUR
TI  - High-Speed and Low Delay Parallel Prefix Adder with Skip Logic
AU  - Botla Mounika
AU  -  K. Sundeep
JO  - International Journal of Scientific Research in Computer Science, Engineering and Information Technology
PB  - Technoscience Academy
DA  - 2018/02/28
PY  - 2018
DO  - https://doi.org/10.32628/IJSRCSEIT
UR  - https://ijsrcseit.com/CSEIT1831301
VL  - 3
IS  - 1
SP  - 1110	
EP  - 1113
AB  - A carry skip adder (CSKA) structure is presented which has lower power consumption with a higher speed. The performance of the conventional CSKA is improved by achieving the speed enhancement by applying concatenation and incrementation schemes. The existed structure utilizes AND-OR-INVERT (AOI) and OR-AND-INVERT (OAI) compound gates for the skip logic. Low power very large scale integration (VLSI) circuits are most significant for designing of high performance and portable devices. The high speed, small area and low cost are the main considerations of VLSI circuits. This paper presents the design and hardware implementation of Hybrid variable latency CSKA. The proposed design is simulated using ISE simulator. The design shows 38% improvement in speed and 11.53% improvement in area compared to carry look ahead adder. The maximum power consumption for proposed system is 0.014W.