TY  - JOUR
TI  - FPGA Realization of Fault Diagnostic and Fault Tolerant Scheme for Digital Circuits
AU  - John Kalloor
AU  -  B. Baskaran
JO  - International Journal of Scientific Research in Computer Science, Engineering and Information Technology
PB  - Technoscience Academy
DA  - 2018/02/28
PY  - 2018
DO  - https://doi.org/10.32628/IJSRCSEIT
UR  - https://ijsrcseit.com/CSEIT183149
VL  - 3
IS  - 1
SP  - 165	
EP  - 172
AB  - The paper echoes to formulate a sequence for injecting, detecting and healing the random occurrence of stuck at faults in combinational circuits. The philosophy involves the immaculate use of an LFSR to generate interconnect fault patterns in the passage of primary inputs of the circuit on their way to the destination. The theory extends to enjoy the benefits of a checker circuit to identify and ensure the presence of faults in an attempt to transcend the corrective action. It engages the artefacts of digital logic principles to evolve a fault tolerant status for the methodology and facilitates to arrive at the fault free output in the presence of faults. The exercise augurs to annihilate the common types of stuck at faults to enhance the reliability in the use of such circuits. The Modelsim platform espouses to pronounce the reality in realizing the nuances of the design in the procedure and avail the artefacts of an FPGA to demonstrate its practical significance.