Manuscript Number : CSEIT1952390

Performance Analysis of Fully Differential Double Tail Dynamic Comparator

Authors(1) :-Priyesh P. Gandhi

This paper presents a novel fully differential double tail dynamic comparator that exhibits lower offset voltage than the conventional dynamic comparators. This paper comprises a novel fully differential double tail high performance comparator suitable for low-voltage low-power applications. A fully differential double tail comparator has been designed to meet the necessity of low offset voltage for optimum power with high speed. The expression for the calculation of the offset voltage of the proposed comparator is derived. These expressions corroborate previously stated results with analytical support as well as providing useful insight for the design of fully differential double tail dynamic comparator by analyzing the influence of each transistor pair individually. Transistor mismatch analysis is carried out for offset voltage to fully explore the trade-offs in the design of comparator. In proposed comparator offset voltage is significantly reduced for optimum power. Authors have proposed novel architecture of dynamic voltage comparator which is differential and double tail and verified the architecture by simulation in 180nm CMOS technology with ±0.9V supply. The Post-layout simulation results illustrates that a comparator designed with the proposed techniques is 45% faster, and 30% more power efficient and exhibits 91% low offset as compared with conventional comparator, which is the fastest among the conventional comparators.

Authors and Affiliations

Priyesh P. Gandhi
Ph. D, Principal, Sigma Institute of Engineering, Vadodara, Gujarat, India

Comparator, Differential Dynamic Comparator (DDC), Fully Differential Double Tail Dynamic Comparator (FDDTDC), Analog to Digital Converters (ADCs), Propagation delay, Offset Voltage, Power Dissipation.

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Publication Details

Published in : Volume 5 | Issue 2 | March-April 2019
Date of Publication : 2019-03-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 1301-1310
Manuscript Number : CSEIT1952390
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

Priyesh P. Gandhi, "Performance Analysis of Fully Differential Double Tail Dynamic Comparator ", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 5, Issue 2, pp.1301-1310, March-April-2019. |          | BibTeX | RIS | CSV

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