Manuscript Number : CSEIT1949170

Design and Implementation of a Multiply-Accumulate (MAC) unit

Authors(2) :-Neethu Johny, Divya Rajan

This paper studies the data-path and VLSI implementation of multiply accumulate (MAC) unit. MAC unit performs multiplication and accumulation process and is an important operation in many of the digital signal processing (DSP) applications. The multiplier is designed using Wallace multiplier and the adder is designed as a carry look ahead adder. The performance analysis of MAC unit is done in terms of area and delay. The design of the MAC model is done in Verilog HDL. The MAC unit is then simulated and synthesized in Xilinx ISE 14.7 for Artix 7 family and the performance analysis is done in terms of area and delay.

Authors and Affiliations

Neethu Johny
Senior Assistant Professor, ECE Department, New Horizon College of Engineering, Bengaluru, India
Divya Rajan
Senior Assistant Professor, ECE Department, New Horizon College of Engineering, Bengaluru, India

Accumulate; High Performance; Carry Look Ahead Adder; Wallace

  1. Chandrakasan, Sheng, & Brodersen, 1992 and Weste & Harris, 3rd Ed.
  2. Deepika, Nidhi Goel “Design of FIR Filter Using Reconfigurable MAC Unit”, 2016 3rd International Conference on Signal Processing and Integrated Networks (SPIN), 2016.
  3. Gitika Bhatia, Karanbir Singh Bhatia, Osheen Chauhan, Soumya Chourasia and Pradeep Kumar “An Efficient MAC Unit with Low Area Consumption”, IEEE INDICON 2015.
  4. Tung Thanh Hoang, Magnus Själander and Per Larsson-Edefors, “A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit”, IEEE Transactions on Circuits and Systems - I : Regular Papers, Vol. 57, No. 12, pp. 3073 – 3081, 2010.
  5. Gitika Bhatia, Karanbir Singh Bhatia, Shashank Srivastava, and Pradeep Kumar “Design and Implementation of MAC Unit Based on Vedic Square, and It’s Application”, IEEE UP Section Conference on Electrical Computer and Electronics, 2015.
  6. S. Ahish, Y.B.N. Kumar, Dheeraj Sharma and M.H. Vasantha, “Design of High Performance Multiply-Accumulate Computation Unit”, Proceedings of IEEE International Advance Computing Conference (IACC), pp. 915-918, 2015.
  7. A. Abdelgawad, “Low Power Multiply Accumulate Unit (MAC) for Future Wireless Sensor Networks”, Proceedings of IEEE Sensors Applications Symposium (SAS), pp.129-132, 2013.
  8. S. Rakesh and K.S. Vijula Grace, “A Survey on the Design and Performance of various MAC Unit Architectures”, Proceedings of IEEE International Conference on Circuits and Systems (ICCS), pp. 312 – 315,2017.

Publication Details

Published in : Volume 4 | Issue 9 | November-December 2019
Date of Publication : 2019-12-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 542-546
Manuscript Number : CSEIT1949170
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

Neethu Johny, Divya Rajan, "Design and Implementation of a Multiply-Accumulate (MAC) unit", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 4, Issue 9, pp.542-546, November-December-2019. |          | BibTeX | RIS | CSV

Article Preview